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Digital signal processing (DSP) has emerged over last two decades as the single most key component in all electronic applications, e.g., multimedia and mobile communications, video compression, digital still and network cameras, mobile phones, radar imaging, acoustic beamformers, GPS, biomedical signal processing etc. Most of these applications impose several challenges in the implementation of DSP systems, like capability to process high throughput data as demanded by the real time application, as well as requiring less power and less chip area.This course aims at providing a comprehensive coverage of some of the important techniques for designing efficient VLSI architectures for DSP. Towards this, architectural optimization at various levels will be considered. The course assumes minimal prerequisites - an undergraduate level knowledge of digital circuit design and elementary DSP operations is sufficient for one to be able to attend the course. Apart from regular students, participants from academia may thus find the course to be useful to develop similar courses at their respective institutions. Alternatively, the course may also be used as a reference by industrial professionals interested in VLSI design of signal processing and communication systems.INTENDED AUDIENCE :Electrical Engg., Electronics and Communication Engg., Instrumentation Engg., Information technology and Computer Science studentsPRE-REQUISITES : NilSUPPORT INDUSTRY : ST Microelectronics Ltd, Texas Instruments, Ittiam Systems
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Week 1 :Graphical representation of DSP algorithms, signal flow graph (SFG), data flow graph (DFG) and dependence graph (DG), high level transformation, critical path.
Week 2 :Retiming of DFG, critical path minimization by retiming, loop retiming and iteration bound
Week 3 :Cutset retiming, design of pipelined DSP architectures, examples
Week 4 :Parallel realization of DSP algorithms, idea of unfolding, unfolding theorem, loop unfolding
Week 5 :Polyphase decomposition of transfer functions, hardware efficient parallel realization of FIR filters, 2-parallel and 3-parallel filter architectures.
Week 6 :Hardware minimization by folding, folding formula, examples from biquad digital filters,
Week 7 :Delay optimization by folding, lifetime analysis, forward-backward data allocation, examples from digital filters
Week 8 :Pipelining digital filters, look ahead techniques, clustered and scattered look ahead, combining parallel processing with pipelining in digital filters
