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This course discussed how a C code can be automatically translated into register transfer level (RTL) design using high-level synthesis (HLS). HLS is an active domain of research in recent times in the domain of electronic Design Automation (EDA) of VLSI. This course will help the student to (i) understand the overall HLS flow, (ii) how a C-code will be converted to its equivalent hardware, (iii) how to write c-code for efficient hardware generation and (iv) how the common software compiler optimization can help to improve the circuit performance. Also, advanced topics like HLS for FPGA targets, HLS for Security, optimizations at RTL level and verification challenges of HLS will be covered. This course will help the student to take up research in the domain of HLS. Also, this course will help the student to become proficient for EDA industries.INTENDED AUDIENCE : Final year BTech Student, MTech and PhD students, engineers from VLSI industriesPREREQUISITES : (1) Basic knowledge of digital design (2) Basic knowledge of Data structures and algorithms (3) Basic knowledge of Verilog. The students may go through the first six lectures of https://nptel.ac.in/courses/106/105/106105083/ to learn Verilog.INDUSTRY SUPPORT : Synopsys, Cadence, Mentor Graphics, Intel, Xilinx
Overview
Syllabus
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Week-1: Introduction to Electronic Design Automation
Week-2: Introduction to C-based VLSI Design: Background Week-3: Introduction to C-based VLSI Design: HLS Flow
Week-4: C-Based VLSI Design: Scheduling Week-5: C-Based VLSI Design: Resource allocation and Binding, Data-path and Controller Generatio Week-6: Efficient Synthesis of C Code
Week-7: Hardware Efficient C Coding
Week-8: Impact of Compiler Optimizations in Hardware Week-9: Verification of High-level Synthesis Week-10: FPGA Technology Mapping Week-11: Securing Design with High-level Synthesis Week-12: Recent Advances in C-Based VLSI Desig
